ISSCC 2003 / SESSION 2 / MULTIMEDIA SIGNAL PROCESSING / PAPER 2.7 2.7 A 1GOPS Reconfigurable Signal Processing IC with Embedded FPGA and 3-Port 1.2GB/s Flash Memory Subsystem

Increasing complexity of system design and shorter time-to-market requirements lead research towards the investigation of hybrid systems including processors enhanced by programmable logic [1][2]. A dynamically reconfigurable processing unit tightly connected to a Flash EEPROM memory subsystem is presented. The reconfigurable processing unit targets image-voice processing and recognition application domains and is implemented by joining a configurable and extensible processor core and an SRAM-based embedded FPGA. Application-specific HW units are added and dynamically modified by embedded FPGA reconfiguration. By implementing application-specific vector processing instructions the unit shows a peak computing power of 1GOPS. Efficient read-writeerase access to code, data and FPGA bitstreams is provided by a specific memory subsystem based on a modular 8Mb, 4-bank Flash memory. It features 3 content-specific I/O ports and delivers an aggregate peak read throughput of 1.2GB/s.